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december 2009 doc id 16917 rev 1 1/42 42 LSM320HAY30 mems motion sensor module: 3d digital accelerometer and 2d pitch and yaw analog gyroscope features 2.7 v to 3.6 v power supply operation low voltage compatible digital ios, 1.8 v 2 g /4 g / 8 g dynamically selectable full-scale 300 dps absolute analog angular rate output i 2 c/spi digital linear acce leration interface (16 bit data output) two separated outputs for pitch and yaw axis (1x and 4x amplified) integrated low-pass filters for angular rate 2 independent programmable interrupt generators for free-fall and motion detection sleep-to-wakeup function 6d orientation detection extended operating temperature range (40 c to +85 c) high stability over temperature high shock survivability embedded self-test embedded power-down embedded low-power mode ecopack ? rohs and ?green? compliant (see section 9 ) applications motion control for smart user interface display orientation gaming and virtual reality input devices industrial and robotics vibration monitoring and compensation impact recognition and logging motion-activated functions intelligent power-saving for handheld devices free-fall detection description the LSM320HAY30 is a low-power system-in- package featuring a 3d digital linear acceleration sensor and a 2d analog angular rate pitch and yaw sensor. it provides excellent temperature stability and high resolu tion over an extended operating temperature range (-40c to +85c). st?s family of sensor modules leverages the robust and mature manufacturing process already used for the production of micromachined accelerometers. the LSM320HAY30 has a dynamically user-selectable full-scale acceleration range of 2 g /4 g /8 g , and an angular rate of 300 dps capable of detecting rates with a -3 db bandwidth up to 140 hz along pitch and yaw axes. the LSM320HAY30 is capable of measuring linear accelerations with output data rates from 0.5 hz up to 1 khz. the embedded self-test capabilit y allows the user to check the functioning of each sensor in the final application. the device can be configured to generate an interrupt signal by inertial wakeup/free-fall events as well as by the position of the device itself. several years ago st successfully pioneered the use of this package for accelerometers. today, st has the widest manufacturing capability an d strongest expertise in the world for production of sensors in plastic lga packages. lga-28l (4.4x7.5x1.1mm) www.st.com
contents LSM320HAY30 2/42 doc id 16917 rev 1 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 pin connection and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 functionality and terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 zero level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.5 advanced features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5.1 linear acceleration sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5.2 angular rate sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 linear acceleration sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 angular rate sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 i2c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1.1 i2c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2 spi bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.1 spi read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2.2 spi write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.2.3 spi read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
LSM320HAY30 contents doc id 16917 rev 1 3/42 8.1 who_am_i (0fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.2 la_ctrl_reg1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.3 la_ctrl_reg2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.4 la_ctrl_reg3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.5 la_ctrl_reg4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.6 la_ctrl_reg5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.7 la_hp_filter_reset (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.8 reference (26h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ) 32 8.9 la_status_reg (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.10 la_out_x_l (28h), la_out_x_h (29h) . . . . . . . . . . . . . . . . . . . . . . . . 33 8.11 la_out_y_l (2ah), la_out_y_h (2bh) . . . . . . . . . . . . . . . . . . . . . . . 33 8.12 la_out_z_l (2ch), la_out_z_h (2dh) . . . . . . . . . . . . . . . . . . . . . . . 33 8.13 la_int1_cfg (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.14 la_int1_src (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.15 la_int1_ths (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.16 la_int1_duration (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.17 la_int2_cfg (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.18 la_int2_src (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.19 la_int2_ths (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.20 la_int2_duration (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
list of tables LSM320HAY30 4/42 doc id 16917 rev 1 list of tables table 1. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5. angular rate sleep mode and power-down mode configuration . . . . . . . . . . . . . . . . . . . . . 14 table 6. external component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 7. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 8. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 9. sad+read/write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 10. transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 11. transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 12. transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 20 table 13. transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 20 table 14. register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 15. who_am_i register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 16. la_ctrl_reg1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 17. la_ctrl_reg1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 18. power mode and low-power output data rate configurations . . . . . . . . . . . . . . . . . . . . . . . 27 table 19. normal mode output data rate configurations and low-pass cut-off frequencies . . . . . . . . 27 table 20. la_ctrl_reg2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 21. la_ctrl_reg2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 22. high-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 23. high-pass filter cut-off frequency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 24. la_ctrl_reg3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 25. la_ctrl_reg3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 26. data signal on int 1 and int 2 pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 27. la_ctrl_reg4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 28. la_ctrl_reg4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 29. la_ctrl_reg5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 30. la_ctrl_reg5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 31. sleep-to-wake configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 32. reference register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 33. reference description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 34. la_status_reg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 35. la_status_reg description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 table 36. la_int1_cfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 37. la_int1_cfg description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 38. interrupt 1 source configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 39. la_int1_src register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 40. la_int1_src description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 41. la_int1_ths register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 42. la_int1_ths description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 43. la_int1_duration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 44. la_int2_duration description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 45. la_int2_cfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 46. la_int2_cfg description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 47. interrupt mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 48. la_int2_src register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
LSM320HAY30 list of tables doc id 16917 rev 1 5/42 table 49. la_int2_src description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 50. la_int2_ths register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 51. la_int2_ths description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 52. la_int2_duration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 53. la_int2_duration description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 54. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 55. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
list of figures LSM320HAY30 6/42 doc id 16917 rev 1 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. LSM320HAY30 electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 4. angular rate output response vs. rotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 figure 5. read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 6. spi read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 7. multiple byte spi read protocol (2 byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 8. spi write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 9. multiple byte spi write protocol (2 byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 10. spi read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 11. lga-28: mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
LSM320HAY30 block diagram and pin description doc id 16917 rev 1 7/42 1 block diagram and pin description figure 1. block diagram #/.42/ , ,/')# ).4%22 504 '%. #,/# + 42)--).' #)2#5 )43 2%&% 2%.# % 3%,& 4%3 4 9 : 9 : 8 8 -58 #3 3#, 30# 3$!3$/3$) 3$/3! +
c : x : : #(!2' % !-0,)&)%2 #(!2'% !-0,)&)%2 #(!2'% !-0 ,)&)% 2 3ensing"lock $%-/$5, !4/2 37 )4#(%$ 8 : ,/7 0!33 #!0 !#)4/2 &) ,4 % 2 $2 )6).' -!3 3 $%-/$5 ,!4/2 37)4#(%$ ,/7 0!33 #!0!# )4/2 &),4%2 &eed b ack l o o p x/548 x/54 : /ptional &i l t er ,0 (0 /ptional &i l t e r ,0 (0 '! ). '!) . /54: notamplified /548n otamplified x x +
: 3ensing)nterface !$ #ontrol ,ogi c $riving-ass $emodul ation converter $) )#30) ).4 ).4 0(!3% '%.%2 !4/2 amplified am plified !-v
block diagram and pin description LSM320HAY30 8/42 doc id 16917 rev 1 1.1 pin connection and description figure 2. pin connection table 1. pin description pin# name function 1 vdd_io power supply for i/o pins 2scl/spci 2 c serial clock (scl)/spi serial port clock (spc) 3 cs spi enable/i 2 c/spi mode selection (1: i 2 c mode; 0: spi enabled) 4 sda/sdi/sdo i 2 c serial data (sda)/spi serial data input (sdi) 3-wire interface serial data output (sdo) 5 sdo/sa0 spi serial data output (sdo)/ i 2 c less significant bit of the device address (sa0) 6 int1 inertial interrupt 1 7 int2 inertial interrupt 2 8 arhp angular rate high-pass filter reset (logic 0: normal operation mode; logic1: external high-pass filter is reset) 9 arpd angular rate power-down (see table 5 ) 10 arst angular rate self-test (see table 5 ) 11 gnd 0 v supply 12 gnd 0 v supply 13 res 0 v supply 14 gnd 0 v supply 15 gnd 0 v supply 16 filtvdd pll filter connection pin 16 17 vcont pll filter connection pin 15 18 out x not amplified out x 9 8 : $)2%#4)/./&4(% $%4 %#4! ",% !##%,%2!4)/.3 : x $%4%#4!",% !. '5,!22!4%3 &),4 6$$ &),4).9 "/44/-6)%7 3#,30# 3$!3$)3$/ ).4 !2(0 6dd?)/ '.$ '.$ ,3-(!9 '.$ !234 ).4 !20$ 3$/3! #3 6$$ 2% 3 2% 3 6#/.4 /54: 62%& 2%3 x).: x/54: x/548 &),46$$ x).8 '.$ /548 '.$ : z !-v
LSM320HAY30 block diagram and pin description doc id 16917 rev 1 9/42 19 4xin x input of 4x amplifier 20 4xout x x rate signal output voltage (amplified) 21 vref reference voltage 22 4x outz z rate signal output voltage (amplified) 23 4xin z input of 4x amplifier 24 out z not amplified out z 25 vdd power supply 26 res connected to vdd 27 res connected to vdd 28 res connected to vdd table 1. pin description (continued) pin# name function
mechanical and electrical specifications LSM320HAY30 10/42 doc id 16917 rev 1 2 mechanical and electrical specifications 2.1 mechanical characteristics @ vdd=3,0 v, t=25 c unless otherwise noted. (a) a. the product is factory calibrated at 3.0 v. the ope rational power supply range is from 2.7 v to 3.6 v. table 2. mechanical characteristics symbol (1) parameter test co nditions min. typ. (2) max. unit la_fs linear acceleration measurement range (3) fs bit set to 00 2.0 g fs bit set to 01 4.0 fs bit set to 11 8.0 ar_fs angular rate measurement range 4x out (amplified) 300 dps out (not amplified) 1200 la_so linear acceleration sensitivity fs bit set to 00 (12 bit) 0.9 1 1.1 mg/digit fs bit set to 01 (12 bit) 1.8 2 2.2 fs bit set to 11 (12 bit) 3.5 3.9 4.3 ar_so angular rate sensitivity (4) 4x out (amplified) 3.33 mv/dps out (not amplified) 0.83 mv/dps la_tcso linear acceleration sensitivity change vs. temperature fs bit set to 00 0.01 %/c ar_tcso angular rate sensitivity change vs temperature delta from 25c 0.07 %/c la_tyoff linear acceleration typical zero- g level offset accuracy (5),(6) fs bit set to 00 20 mg la_tcoff linear acceleration zero- g level change vs. temperature max delta from 25c 0.1 mg/c ar_zrl zero-rate level (6) 1.5 v ar_vref reference voltage 1.5 v ar_tczrl angular rate zero-rate level change vs. temperature max delta from 25c 0.05 dps/c la_an linear acceleration noise density fs bit set to 00 218 g/ hz ar_rn angular rate noise density 0.02 dps/ hz ar_nl angular rate non linearity best fit straight line 1 % fs la_bw linear acceleration bandwidth (7) odr/2 hz ar_bw angular rate bandwidth (8) 140 hz la_st linear acceleration self-test output change (9),(10),(11) fs bit set to 00 x axis +500 lsb fs bit set to 00 y axis -500 lsb fs bit set to 00 z axis +600 lsb
LSM320HAY30 mechanical and electrical specifications doc id 16917 rev 1 11/42 2.2 electrical characteristics @ vdd=3,0 v, t=25 c unless otherwise noted. (b) ar_st angular rate self-test output change 250 mv top operating temperature range -40 +85 c 1. linear acceleration (la), angular rate (ar) parameter labeling 2. typical specificat ions are not guaranteed 3. verified by wafer level test and measur ement of initial offset and sensitivity 4. sensitivity and zero-rate offset ar e not ratiometric to supply voltage 5. typical zero- g level offset value after msl3 preconditioning 6. offset can be eliminated by enabl ing the built-in high-pass filter 7. refer to table 23 for filter cut-off frequency. 8. the product is capable of measuring angular rates extending from dc to the selected bw. 9. the sign of ?self-test output change? is defined by la_ctrl_reg4 stsign bit ( table 27 ), for all axes. 10. linear acceleration sensing self-test output changes with the power supply. ?self-test output change? is defined as output[lsb] (la_ctrl_reg4 st bit=1) - output[lsb] (la_ctrl_reg4 st bit=0) . 1lsb=4g/4096 at 12bit representation, 2 g full-scale 11. output data reach 99% of final value after 1/odr+1ms when enabling linear acceleration sensing self-test mode, due to device filtering. table 2. mechanical characteristics (continued) symbol (1) parameter test co nditions min. typ. (2) max. unit b. the product is factory calibrated at 3 v. table 3. electrical characteristics symbol parameter test condition min. typ. (1) max. unit vdd supply voltage 2.7 3.0 3.6 v vdd_io i/o pins supply voltage (2) 1.71 vdd+0.1 v la_idd linear acceleration current consumption in normal mode odr = 50 hz 0.25 ma ar_idd angular rate current consumption in normal mode arpd pin connected to gnd 6.8 ma la_iddlp linear acceleration current consumption in low-power mode odr lp = 0.5 hz 10 a ar_iddsl angular rate current consumption in sleep mode arpd, arst pin connected to vdd 2.1 5 ma la_iddpdn linear acceleration current consumption in power-down mode 1a ar_iddpdn angular rate current consumption in power-down mode arpd pin connected to vdd 15a
mechanical and electrical specifications LSM320HAY30 12/42 doc id 16917 rev 1 ar_v st angular rate self-test input logic 0 level 0 0.2*vdd v logic 1 level 0.8*vdd vdd ar_v pd angular rate power-down input logic 0 level 0 0.2*vdd v logic 1 level 0.8*vdd vdd la_vih linear acceleration digital high level input voltage 0.8*vdd_io v la_vil linear acceleration digital low level input voltage 0.2*vdd_io v la_voh linear acceleration high level output voltage 0.9*vdd_io v la_vol linear acceleration low level output voltage 0.1*vdd_io v la_odr linear acceleration output data rate in normal mode dr bit set to 00 50 hz dr bit set to 01 100 dr bit set to 10 400 dr bit set to 11 1000 la_odr lp linear acceleration output data rate in low-power mode pm bit set to 010 0.5 hz pm bit set to 011 1 pm bit set to 100 2 pm bit set to 101 5 pm bit set to 110 10 la_ton linear acceleration turn-on time (3) odr = 100 hz 1/odr+1 ms s ar_ton angular rate turn-on time (4) 200 ms top operating temperature range -40 +85 c 1. typical specificat ions are not guaranteed 2. it is possible to remove vdd, maintaining vdd_io wit hout blocking the communication buses. in this condition the measurement chain is powered off. 3. time to obtain valid data after exiting power-down mode 4. time to obtain valid data after exiting power-down mode table 3. electrical characteristics (continued) symbol parameter test condition min. typ. (1) max. unit
LSM320HAY30 absolute maximum ratings doc id 16917 rev 1 13/42 3 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 4. absolute maximum ratings symbol ratings maximum value unit vdd supply voltage -0.3 to 4.8 v vin input voltage on any control pin (pd, st) -0.3 to vdd +0.3 v a acceleration 3000 for 0.5 ms g 10000 for 0.1 ms g vdd_io i/o pin supply voltage -0.3 to 6 v vin input voltage on any control pin (cs, scl/spc, sda/sdi/sdo, sdo/sa0) -0.3 to vdd_io +0.3 v a pow acceleration (any axis, powered, vdd = 3 v) 3000 for 0.5 ms g 10000 for 0.1 ms g a unp acceleration (any axis, unpowered) 3000 for 0.5 ms g 10000 for 0.1 ms g t op operating temperature range -40 to +85 c t stg storage temperature range -40 to +125 c esd electrostatic discharge protection 2 (hbm) kv this is a mechanical shock sensitive device, improper handling can cause permanent damage to the part. this is an esd sensitive device, improper handling can cause permanent damage to the part.
functionality and terminology LSM320HAY30 14/42 doc id 16917 rev 1 4 functionality and terminology the LSM320HAY30 is an inertial module capable of detecting 3-axis linear acceleration and 2-axis angular rate. the system is housed in an lga package. the device includes an asic with a digital ic interface capable of providing linear acceleration information through an i 2 c/spi serial interface and analog output related to angular rate. the LSM320HAY30 may also be configured to generate an inertial wakeup and free-fall interrupt signal according to a programmed acceleration event along the enabled axes. both free-fall and wakeup can be used simultaneously on two different pins (int1/int2). 4.1 factory calibration the system is factory calibrated for sensitivit y and zero level. the trimming values are stored inside the device in non-volatile memory. when the device is turned on, the trimming parameters are downloaded into the registers to be used during active operation. this allows the use of the device without further calibration. 4.2 sensitivity linear acceleration sensing liner acceleration sensitivity (la_so) describes the gain of the sensor and can be determined e.g. by applying 1 g acceleration to it. because the sensor can measure dc accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the output value again. by doing so, a 1 g acceleration is applied to the sensor. subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. this value changes very little over temperature and over time. the sensitivity tolerance describes the range of sensitivities of a large number of sensors. angular rate sensing angular rate detection produces a positive-going output voltage for counter-clockwise rotation around the sensitive axis considered . angular rate sensitiv ity (ar_so) describes the gain of the sensor and can be determined by applying a defined angular rate to it. this value changes very little over temperature and over time. 4.3 zero level zero- g level zero- g level offset (la_tyoff) describes the deviation of an actual output signal from the ideal output signal if no linear acceleration is present. a sensor in a steady state on a horizontal surface will measure 0 g on both the x and y axes , whereas the z axis will measure 1 g . ideally, the output is in the middle of the dynamic range of the sensor (content
LSM320HAY30 functionality and terminology doc id 16917 rev 1 15/42 of out registers 00h, data expressed as 2?s complement number). a deviation from the ideal value in this case is called zero- g offset. offset is to some extent a result of stress to the mems sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. zero- g level offset changes little over temperature, see ?zero- g level change vs. temperature? (la_tcoff) in table 2 . the zero- g level tolerance (la_tyoff) describes the standard deviation of the range of zero- g levels of a group of sensors. zero-rate level angular rate zero-rate level (ar_zrl) describes the actual angular rate output signal if there is no angular rate present. zero-rate level of precise mems sensors is, to some extent, a result of stress to the sensor and therefore zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. this value changes very little over temperature and time. 4.4 self-test linear acceleration self-test self-test allows the checking of sensor functionality without moving it. the self-test function is off when the self-test bit (st) of la_ctrl_reg4 (control register 4) is programmed to ?0?. when the self-test bit of la_ctrl_reg4 is programmed to ?1? an actuation force is applied to the sensor, simulating a definite input acce leration. in this case, the sensor outputs will exhibit a change in their dc levels which are related to the selected full-scale through the device sensitivity. when self-test is activate d, the device output level is given by the algebraic sum of the signals produced by the ac celeration acting on the sensor and by the electrostatic test-force. if the output signals change within the amplitude specified in table 2 , then the sensor is working properly and the parameters of the interface chip are within the defined specifications. angular rate self-test self-test allows testing of the mechanical and electric parts of the sensor, permitting the seismic mass to be moved by means of an electrostatic test-force. the self-test function is off when the arst pin is connected to gnd. when the arst pin is tied to vdd and arpd is tied to gnd (see table 5 ), an actuation force is applied to the sensor, emulating a definite coriolis force. in this case the sensor output exhibits a voltage change in its dc level which is also dependent on the supply voltage. when st is active, the device output level is given by the algebraic sum of the signals produced by the velocity acting on the sensor and by the electrostatic test-force. if the output signals change within the amplitude specified in table 2 , then the mechanical element is working properly and the parameters of the interface chip are within the defined specifications.
functionality and terminology LSM320HAY30 16/42 doc id 16917 rev 1 4.5 advanced features 4.5.1 linear ac celeration sensing the LSM320HAY30 linear acceleration sensor includes a low-power mode characterized by lower data rate refreshing. in this way the device, even when sleeping, continues sensing acceleration and generating interrupt requests. the ?sleep-to-wakeup? function, in conjunction with low-power mode, allows further reduction of system power consumption and the development of new smart applications. when the sleep-to-wakeup function is activated,the LSM320HAY30 is able to automatically wake up the linear acceleration sensor as soon as an interrupt event has been detected. with this feature the system is efficiently switched from low-power mode to normal mode based on user-selectable positioning and acce leration events, thus ensuring power-saving and flexibility. 4.5.2 angular rate sensing sleep mode, self-test and power-down the LSM320HAY30 has advanced power-saving features for angular rate sensing thanks to the availability of three differ ent operating modes. when the device is set to sleep mode configuration, the reading chain is completely turned off, resuting in low power consumption. in this condition, the device turn-on time is significantly reduced, allowing simple external power cycling. based on the table below, the user can select the desired operating mode using two dedicated pins (arst and arpd). high-pass filter reset (arhp) the LSM320HAY30 provides the possibility to reset the option al external high-pass filter by applying a high logic value to the arhp p ad. this procedure ensures faster response, especially during overload conditions. moreover, this operation is recommended each time the device is powered. table 5. angular rate sleep mode and power-down mode configuration operating mode arst pin arpd pin normal mode 0 0 power-down 0 1 self-test 1 0 sleep mode 1 1
LSM320HAY30 application hints doc id 16917 rev 1 17/42 5 application hints figure 3. LSM320HAY30 electrical connections table 6. external component values component type component value capacitor c1 4.7 f c2 2.2 nf to 2.2 f c3 470 nf c4 10 nf c5 100 nf c6 10 f resistor r1 1 m ? r2 33 k ? r3 10 k ? f digit a l s ign a l from/to s ign a l controller. s ign a l? s level s a re defined b y proper s election of vdd_io y 1 x z direction of detectable acceleration s direction of detectable angular rate filtvdd filtin y (top view) 24 1 arhp re s gnd l s m 3 20hay 3 0 gnd 2 8 ar s t 10 15 11 14 25 arpd vdd re s re s vcont re s gnd gnd 4xin x out x recommended low-p ass filter option a l high-p ass filter vref gnd c1 r1 c2 r2 filtvdd r 3 c 3 c4 vref gnd c1 r1 c2 r2 out z 4xin z vref 4xouty 4xoutx vdd_io s cl/ s pc c s s da/ s di/ s do s do/ s a0 int1 int2 vdd c6 c5 y 1 x z +? x +? z option a l high-p ass filter recommended low-p ass filter am06041v1
application hints LSM320HAY30 18/42 doc id 16917 rev 1 the device core is supplied through the vdd line. power supply decoupling capacitors (c1=100 nf ceramic, c2=10 f aluminum) should be placed as near as possible to the supply pin of the device (common design practice). all voltage and ground supplies must be present at the same time to obtain proper behavior of the ic (refer to figure 3 ). 5.1 linear acceleration sensing the functionality of the device and the measured acceleration data is selectable and accessible through the spi/i 2 c interface. the functions, the threshold and the timing of the two interrupt pins (int 1 and int 2) can be completely programmed by the user though the spi/i 2 c interface. 5.2 angular rate sensing the LSM320HAY30 allows band limitation of the output rate response through the use of an external low-pass filter (recommended) and/or high-pass filter (optional) in addition to the embedded low-pass filter (f t = 140 hz). 4xoutx and 4xoutz are, respectively, outx and outz amplified outputs lines, internally buffered to ensure low output impedance. if external filtering is not applied, it is mandatory to short-circuit pad 18 to pad 19 and pad 23 to pad 24, respectively, when amplified outputs are used. when only a non-amplified output is used (outx/outz), it is recommended to set pin 19 and 23 to a fixed reference voltage (vref). the LSM320HAY30 ic includes a pll (phase locked loop) circuit to synchronize driving and sensing interfaces. capacitors and resistors must be added at the filtvdd and vcont pins (as shown in figure 3 ) to implement a second-order low-pass filter. figure 4. angular rate output response vs. rotation s te a dy s t a te po s ition: 4xoutx = 4xoutz = 1.5v outx = outz = 1.5v po s itive rot a tion s as indic a ted b y the a rrow s + 3 00/ s ec --> 4xoutx, 4xoutz = 1.5v + s oa *3 00 = 2.5v + 3 00/ s ec --> outx, outz = 1.5v + s o *3 00 = 1.75v incre as e o u tp u t v a l u e over zero r a te level: 1 z y 1 x z +? x +? z am06042v1
LSM320HAY30 application hints doc id 16917 rev 1 19/42 5.3 soldering information the lga package is compliant with the ecopack ? , rohs and ?green? standard. it is qualified for soldering heat resist ance according to jedec j-std-020. leave ?pin 1 indicator? unconnected during soldering. land pattern and soldering recommendations are available at www.st.com.
digital interfaces LSM320HAY30 20/42 doc id 16917 rev 1 6 digital interfaces the registers embedded in the LSM320HAY30 may be accessed through both the i 2 c and spi serial interfaces. the latter may be software configured to operate either in 3-wire or 4- wire interface mode. the serial interfaces are mapped onto the same pads. to select/exploit the i 2 c interface, the cs line must be tied high (i.e. connected to vdd_io). 6.1 i 2 c serial interface the LSM320HAY30 i 2 c is a bus slave. the i 2 c is employed to write data into registers whose content can also be read back. the relevant i 2 c terminology is given in the table below. there are two signals associated with the i 2 c bus: the serial clock line (scl) and the serial data line (sda). the latter is a bidirectional line used for sending and receiving the data to/from the interface. both the lines are connected to vdd_io through a pull-up resistor embedded inside the LSM320HAY30. when the bus is free, both the lines are high. the i 2 c interface is compliant with fast mode (400 khz) i 2 c standards as well as with normal mode. table 7. serial interface pin description pin name pin description cs spi enable i 2 c/spi mode selection (1: i 2 c mode; 0: spi enabled) scl spc i 2 c serial clock (scl) spi serial port clock (spc) sda sdi sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) sa0 sdo i 2 c less significant bit of the device address (sa0) spi serial data output (sdo) table 8. serial interface pin description term description transmitter the device which sends data to the bus receiver the device which receives data from the bus master the device which initiates a transfer, generates clock signals and terminates a transfer slave the device addressed by the master
LSM320HAY30 digital interfaces doc id 16917 rev 1 21/42 6.1.1 i 2 c operation the transaction on the bus is started through a start (st) signal. a start condition is defined as a high to low transition on the data line while the scl line is held high. after this has been transmitted by the master, the bus is considered busy. the next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the 8th bit tells whether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in the system compares the first seven bits after a start condition with its address. if they match, the device considers itself addressed by the master. the slave address (sad) associated with the LSM320HAY30 is 001100xb. the sdo / sa0 pad can be used to modify the least significan t bit of the device address. if the sa0 pad is connected to voltage supply, lsb is ?1? (address 0011001b), otherwise if the sa0 pad is connected to ground, the lsb value is ?0? (address 0011000b). this solution permits connecting and addressing two different accelerometers to the same i 2 c lines. data transfer with acknowledge is mandatory. the transmitter must release the sda line during the acknowledge pulse. the receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. a receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. the i 2 c embedded in the LSM320HAY30 behaves like a slave device and the following protocol must be adhered to. after the start condition (st) a slave address is sent. once a slave acknowledge (sak) has been returned, an 8-bit sub-a ddress (sub) is transmitted: the 7 lsb represent the actual register address while the msb enables address auto-increment. if the msb of the sub field is ?1?, the sub (register address) is automatically incremented to allow multiple data read/write. the slave address is completed with a read/write bit. if the bit was ?1? (read), a repeated start (sr) condition will have to be issued after the two sub-addr ess bytes; if the bit is ?0? (write) the master transmits to the slave with direction unchanged. table 9 explains how the sad+read/write bit pattern is composed, listing all the possible configurations. table 9. sad+read/write patterns command sad[6:1] sad[0] = sa0 r/w sad+r/w read 001100 0 1 00110001 (31h) write 001100 0 0 00110000 (30h) read 001100 1 1 00110011 (33h) write 001100 1 0 00110010 (32h) table 10. transfer when master is writing one byte to slave master st sad + w sub data sp slave sak sak sak
digital interfaces LSM320HAY30 22/42 doc id 16917 rev 1 data are transmitted in byte format (data). each data transfer contains 8 bits. the number of bytes transferred per transfer is unlimited. data is transferred with the most significant bit (msb) first. if a receiver cannot receive another complete byte of data until it has performed some other function, it can hold the clock line scl low to force the transmitter into a wait state. data transfer only continues when the receiver is ready for another byte and releases the data line. if a slave receiver does not acknowledge the slave address (i.e. it is not able to receive because it is performing a real-time function) the data line must be left high by the slave. the master can then abort the transfer. a low to high transition on the sda line while the scl line is high is defined as a stop condition. each data transfer must be terminated by the generation of a stop (sp) condition. in order to read multiple bytes, it is necessary to assert the most significant bit of the sub- address field. in other words, sub(7) must be equal to 1 while sub(6-0) represents the address of the first register to be read. in the presented communication format mak is master acknowledge and nmak is no master acknowledge. 6.2 spi bus interface the LSM320HAY30 spi is a bus slave. the spi allows writing and reading of the registers of the device. the serial interface interacts with the outside world with 4 wires: cs , spc , sdi and sdo . table 11. transfer when master is writing multiple bytes to slave master st sad + w sub data data sp slave sak sak sak sak table 12. transfer when master is receiving (reading) one byte of data from slave master st sad + w sub sr sad + r nmak sp slave sak sak sak data table 13. transfer when master is receiving (reading) multiple bytes of data from slave master st sad+w sub sr sad+r mak mak nmak sp slave sak sak sak data data data
LSM320HAY30 digital interfaces doc id 16917 rev 1 23/42 figure 5. read and write protocol cs is the serial port enable and is controlled by the spi master. it goes low at the start of the transmission and goes back high at the end. spc is the serial port clock and is controlled by the spi master. it is stopped high when cs is high (no transmission). sdi and sdo are respectively the serial port da ta input and output. these lines are driven at the falling edge of spc and should be captured at the rising edge of spc . both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multip le bytes read/write. bit duration is the time between two falling edges of spc . the first bit (bit 0) starts at the first falling edge of spc after the falling edge of cs while the last bit (bit 15, bit 23, ...) starts at the last falling edge of spc just before the rising edge of cs . bit 0 : rw bit. when 0, the data di(7:0) is written to the device. when 1, the data do(7:0) from the device is read. in the latter case, the chip drives sdo at the start of bit 8. bit 1 : ms bit. when 0, the address remains unchanged in multiple read/write commands. when 1, the address is auto incremented in multiple read/write commands. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written into the device (msb first). bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). in multiple read/write commands, further blocks of 8 clock periods are added. when the ms bit is ?0? the address used to read/write data remains the same for every block. when the ms bit is ?1? the address used to read/write data is incremented at every block. the function and the behavior of sdi and sdo remain unchanged. 6.2.1 spi read figure 6. spi read protocol cs spc sdi sdo rw ad5 ad4 ad3 ad2 ad1 ad0 di7di6di5di4di3di2di1di0 do7do6do5do4do3do2do1do0 ms cs spc sdi sdo rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ms
digital interfaces LSM320HAY30 24/42 doc id 16917 rev 1 the spi read command is performed with 16 clock pulses. a multiple byte read command is performed adding blocks of 8 clock pulses after the previous one. bit 0 : read bit. the value is 1. bit 1 : ms bit. when 0, do not increment the address. when 1, increment the address in multiple reading. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). bit 16-... : data do(...-8). further da ta in multiple byte reading. figure 7. multiple byte spi read protocol (2 byte example) 6.2.2 spi write figure 8. spi write protocol the spi write command is performed with 16 clock pulses. a multiple byte write command is performed adding blocks of 8 clock pulses after the previous one. bit 0 : write bit. the value is 0. bit 1 : ms bit. when 0, do not increment the address. when 1, increment the address in multiple writing. bit 2 -7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written to the device (msb first). bit 16-... : data di(...-8). further data in multiple byte writing. cs spc sdi sdo rw do7do6do5do4do3do2do1do0 ad5 ad4 ad3 ad2 ad1 ad0 do15 do14 do13 do12 do11 do10 do9 do8 ms cs spc sdi rw di7 di6 di5 di4 di3 di2 di1 di0 ad5 ad4 ad3 ad2 ad1 ad0 ms
LSM320HAY30 digital interfaces doc id 16917 rev 1 25/42 figure 9. multiple byte spi write protocol (2 byte example) 6.2.3 spi read in 3-wires mode 3-wires mode is entered by sett ing to ?1? bit sim (spi serial interface mode selection) in la_ctrl_reg4. figure 10. spi read protocol in 3-wires mode the spi read command is performed with 16 clock pulses: bit 0 : read bit. the value is 1. bit 1 : ms bit. when 0, do not increment the address. when 1, increment the address in multiple reading. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). multiple read command is also available in 3-wires mode. cs spc sdi rw ad5 ad4 ad3 ad2 ad1 ad0 di7 di6 di5 di4 di3 di2 di1 di0 di15 di14 di13 di12 di11 di10 di9 di8 ms cs spc sdi/o rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ms
register mapping LSM320HAY30 26/42 doc id 16917 rev 1 7 register mapping the table given below provides a listing of the 8-bit registers embedded in the device and the related addresses: table 14. register address map name type register address default comment hex binary reserved (do not modify) 00 - 0e reserved who_am_i r 0f 000 1111 00110010 dummy register reserved (do not modify) 10 - 1f reserved la_ctrl_reg1 rw 20 010 0000 00000111 la_ctrl_reg2 rw 21 010 0001 00000000 la_ctrl_reg3 rw 22 010 0010 00000000 la_ctrl_reg4 rw 23 010 0011 00000000 la_ctrl_reg5 rw 24 010 0100 00000000 la_hp_filter_reset r 25 010 0101 dummy register la_reference rw 26 010 0110 00000000 la_status_reg r 27 010 0111 00000000 la_out_x_l r 28 010 1000 output la_out_x_h r 29 010 1001 output la_out_y_l r 2a 010 1010 output la_out_y_h r 2b 010 1011 output la_out_z_l r 2c 010 1100 output la_out_z_h r 2d 010 1101 output reserved (do not modify) 2e - 2f reserved la_int1_cfg rw 30 011 0000 00000000 la_int1_source r 31 011 0001 00000000 la_int1_ths rw 32 011 0010 00000000 la_int1_duration rw 33 011 0011 00000000 la_int2_cfg rw 34 011 0100 00000000 la_int2_source r 35 011 0101 00000000 la_int2_ths rw 36 011 0110 00000000 la_int2_duration rw 37 011 0111 00000000 reserved (do not modify) 38 - 3f reserved
LSM320HAY30 register mapping doc id 16917 rev 1 27/42 registers marked as reserved must not be changed. writing to these registers may cause permanent damage to the device. the content of the registers that are loaded at boot should not be changed. they contain the factory calibrated values. their content is automatically restored when the device is powered up.
register description LSM320HAY30 28/42 doc id 16917 rev 1 8 register description the device contains a set of registers which are used to control acceleration portion behavior and to retrieve acceleration data. the register address, composed of 7 bits, is used to identify them and to write the data through the serial interface. 8.1 who_am_i (0fh) this register is the device identification register , and contains the device identifier which, for the LSM320HAY30, is set to 32h. 8.2 la_ctrl_reg1 (20h) pm bits allow selection between power-down and two operating active modes. the device is in power-down mode when the pd bits are set to ?000? (default value after boot). table 18 shows all the possible power mode configurations and respective output data rates. output data in the low-power modes are computed with a low-pass filter cut-off frequency defined by dr1, dr0 bits. dr bits, in normal mode operation, select the data rate at which acceleration samples are produced. in low-power mode they define the output data resolution. table 19 shows all the possible configurations for the dr1 and dr0 bits. table 15. who_am_i register 00110010 table 16. la_ctrl_reg1 register pm2 pm1 pm0 dr1 dr0 zen yen xen table 17. la_ctrl_reg1 description pm2 - pm0 power mode selection. default value: 000 (000: power-down; others: refer to table 18 ) dr1, dr0 data rate selection. default value: 00 (00:50 hz; others: refer to table 19 ) zen z axis enable. default value: 1 (0: z axis disabled; 1: z axis enabled) ye n y axis enable. default value: 1 (0: y axis disabled; 1: y axis enabled) xen x axis enable. default value: 1 (0: x axis disabled; 1: x axis enabled)
LSM320HAY30 register description doc id 16917 rev 1 29/42 8.3 la_ctrl_reg2 (21h) table 18. power mode and low-power output data rate configurations pm2 pm1 pm0 power mode selection output data rate [hz] odr lp 0 0 0 power-down -- 0 0 1 normal mode odr 010 low power 0.5 011 low power 1 100 low power 2 101 low power 5 110 low power 10 table 19. normal mode output data rate configurations and low-pass cut-off frequencies dr1 dr0 output data rate [hz] odr low-pass filter cut-off frequency [hz] 00 50 37 01 100 74 1 0 400 292 1 1 1000 780 table 20. la_ctrl_reg2 register boot hpm1 hpm0 fds hpen2 hpen1 hpcf1 hpcf0 table 21. la_ctrl_reg2 description boot reboot memory content. default value: 0 (0: normal mode; 1: reboot memory content) hpm1, hpm0 high-pass filter mode selection. default value: 00 (00: normal mode. others: refer to table 22 ) fds filtered data selection. default value: 0 (0: internal filter bypassed; 1: data from internal filter sent to output register) hpen2 high-pass filter enabled for interrupt 2 source. default value: 0 (0: filter bypassed; 1: filter enabled)
register description LSM320HAY30 30/42 doc id 16917 rev 1 the boot bit is used to refresh the content of the internal registers stored in the flash memory block. at device power-up, the content of the flash memory block is transferred to the internal registers related to trimming functions to permit good device behavior. if, for any reason, the content of the trimming registers was changed, it is sufficient to use this bit to restore the correct values. when the boot bit is set to ?1?, the content of internal flash is copied to the corresponding internal registers and is used to calibrate the device. these values are factory-trimmed and are different for every accelerometer. they permit good device behavior and normally do not have to be modified. at the end of the boot process, the boot bit is again set to ?0?. hpcf[1:0] . these bits are used to configure the high-pass filter cut-off frequency f t which is given by: the equation can be simplified to the following approximated equation: hpen1 high-pass filter enabled for interrupt 1 source. default value: 0 (0: filter bypassed; 1: filter enabled) hpcf1, hpcf0 high-pass filter cut-off frequency c onfiguration. default value: 00 (00: hpc=8; 01: hpc=16; 10: hpc=32; 11: hpc=64) table 22. high-pass filter mode configuration hpm1 hpm0 high-pass filter mode 0 0 normal mode (reset reading hp_reset_filter) 0 1 reference signal for filtering 1 0 normal mode (reset reading hp_reset_filter) table 23. high-pass filter cut-off frequency configuration hpcoeff2,1 f t [hz] data rate = 50 hz f t [hz] data rate = 100 hz f t [hz] data rate = 400 hz f t [hz] data rate = 1000 hz 00 1 2 8 20 01 0.5 1 4 10 10 0.25 0.5 2 5 11 0.125 0.25 1 2.5 table 21. la_ctrl_reg2 description (continued) f t 1 1 hpc ----------- - ? ?? ?? f s 2 ------ ? ln = f t f s 6hpc ? ---------------------- =
LSM320HAY30 register description doc id 16917 rev 1 31/42 8.4 la_ctrl_reg3 (22h) 8.5 la_ctrl_reg4 (23h) table 24. la_ctrl_reg3 register ihl pp_od lir2 i2_cfg1 i2_cfg0 lir1 i1_cfg1 i1_cfg0 table 25. la_ctrl_reg3 description ihl interrupt active high, low. default value: 0 (0: active high; 1: active low) pp_od push-pull/open drain selection on interrupt pad. default value 0. (0: push-pull; 1: open drain) lir2 latch interrupt request on int2_src register, with int2_src register cleared by reading int2_src itself. default value: 0. (0: interrupt request not latched; 1: interrupt request latched) i2_cfg1, i2_cfg0 data signal on int 2 pad control bits. default value: 00. (see table below) lir1 latch interrupt request on int1_src register, with int1_src register cleared by reading int1_src register. default value: 0. (0: interrupt request not latched; 1: interrupt request latched) i1_cfg1, i1_cfg0 data signal on int 1 pad control bits. default value: 00. (see table below) table 26. data signal on int 1 and int 2 pad i1(2)_cfg1 i1(2)_cfg0 int 1(2) pad 0 0 interrupt 1 (2) source 0 1 interrupt 1 source or interrupt 2 source 1 0 data ready 1 1 boot running table 27. la_ctrl_reg4 register bdu ble fs1 fs0 stsign 0 st sim
register description LSM320HAY30 32/42 doc id 16917 rev 1 the bdu bit is used to inhibit output register updates between the reading of the upper and lower register parts. in default mode (bdu = ?0?), the lower and upper register parts are updated continuously. if it is not certain to read faster than the output data rate, it is recommended to set bdu bit to ?1?. in this way, after the reading of the lower (upper) register part, the content of that output register is not updated until the upper (lower) part is read also. this feature avoids reading lsb and msb related to different samples. 8.6 la_ctrl_reg5 (24h) turnon bits are used for turning on the sleep-to-wake function. table 28. la_ctrl_reg4 description bdu block data update. default value: 0 (0: continuous update; 1: output registers not updated between msb and lsb reading) ble big/little endian data selection. default value 0. (0: data lsb @ lower address; 1: data msb @ lower address) fs1, fs0 full-scale selection. default value: 00. (00: 2 g ; 01: 4 g ; 11: 8 g ) stsign self-test sign. default value: 00. (0: self-test plus; 1 self-test minus) st self-test enable. default value: 0. (0: self-test disabled; 1: self-test enabled) sim spi serial interface mode selection. default value: 0. (0: 4-wire interface; 1: 3-wire interface) table 29. la_ctrl_reg5 register 000000turnon1turnon0 table 30. la_ctrl_reg5 description tu r n o n 1 , tu r n o n 0 turn-on mode selection for sleep-to-wake function. default value: 00. table 31. sleep-to-wake configuration turnon1 turnon0 sl eep-to-wake status 0 0 sleep-to-wake function is disabled 11 turned on: the device is in low-power mode (odr is defined in la_ctrl_reg1)
LSM320HAY30 register description doc id 16917 rev 1 33/42 by setting the turnon[1:0] bits to 11, the ?sleep-to-wake? function is enabled. when an interrupt event occurs, the device is goes into normal mode, increasing the odr to the value defined in la_ctrl_reg1. although the device is in normal mode, la_ctrl_reg1 content is not automatically changed to ?normal mode? configuration. 8.7 la_hp_filter_reset (25h) dummy register. reading at this address instantaneously zeroes the content of the internal high-pass filter. if the high-pass filter is enabled, all three axes are instantaneously set to 0 g . this makes it possible to surmount the settling time of the high-pass filter. 8.8 reference (26h) this register sets the acceleration value taken as a reference for the high-pass filter output. when the filter is turned on (at least one fds, hpen2, or hpen1 bit is equal to ?1?) and hpm bits are set to ?01?, filter out is generated taking this value as a reference. 8.9 la_status_reg (27h) table 32. reference register ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 table 33. reference description ref7 - ref0 reference value for high-pass filter. default value: 00h. table 34. la_status_reg register zyxor zor yor xor zyxda zda yda xda table 35. la_status_reg description zyxor x, y and z axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data has overwritten the pr evious one before it was read) zor z axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the z-axis ha s overwritten the previous one) yor y axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the y-axis has overwritten the previous one)
register description LSM320HAY30 34/42 doc id 16917 rev 1 8.10 la_out_x_l (28h), la_out_x_h (29h) x-axis acceleration data. the value is expressed as two?s complement. 8.11 la_out_y_l (2ah), la_out_y_h (2bh) y-axis acceleration data. the value is expressed as two?s complement. 8.12 la_out_z_l (2ch), la_out_z_h (2dh) z-axis acceleration data. the value is expressed as two?s complement. 8.13 la_int1_cfg (30h) xor x axis data overrun. default value: 0 (0: no overrun has occurred; 1: new data for the x-axis has overwritten the previous one) zyxda x, y and z axis new data available. default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) zda z axis new data available. default value: 0 (0: new data for the z-axis is not yet available; 1: new data for the z-axis is available) yda y axis new data available. default value: 0 (0: new data for the y-axis is not yet available; 1: new data for the y-axis is available) xda x axis new data available. default value: 0 (0: new data for the x-axis is not yet available; 1: new data for the x-axis is available) table 35. la_status_reg description (continued) table 36. la_int1_cfg register aoi 6d zhie zlie yhie ylie xhie xlie table 37. la_int1_cfg description aoi and/or combination of interrupt events. default value: 0. (see table 38 ) 6d 6 direction detection function enable. default value: 0. (see table 38 ) zhie enable interrupt generation on z high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold)
LSM320HAY30 register description doc id 16917 rev 1 35/42 configuration register for interrupt 1 source. 8.14 la_int1_src (31h) zlie enable interrupt generation on z low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) yhie enable interrupt generation on y high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) ylie enable interrupt generation on y low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) xhie enable interrupt generation on x high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) xlie enable interrupt generation on x low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) table 38. interrupt 1 source configurations aoi 6d interrupt mode 0 0 or combination of interrupt events 0 1 6 direction move ment recognition 1 0 and combination of interrupt events 1 1 6 direction position recognition table 37. la_int1_cfg description (continued) table 39. la_int1_src register 0 ia zhzlyhylxhxl table 40. la_int1_src description ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) zh z high. default value: 0 (0: no interrupt, 1: z high event has occurred) zl z low. default value: 0 (0: no interrupt; 1: z low event has occurred) yh y high. default value: 0 (0: no interrupt, 1: y high event has occurred)
register description LSM320HAY30 36/42 doc id 16917 rev 1 interrupt 1 source register. read-only register. reading at this address clears la_int1_src ia bit (and the interrupt signal on int 1 pin) and allows the refreshing of data in the la_int1_src register if the latched option was chosen. 8.15 la_int1_ths (32h) 8.16 la_int1_duration (33h) the d6 - d0 bits set the minimum duration of the interrupt 2 event to be recognized. duration steps and maximum values depend on the odr chosen. 8.17 la_int2_cfg (34h) yl y low. default value: 0 (0: no interrupt, 1: y low event has occurred) xh x high. default value: 0 (0: no interrupt, 1: x high event has occurred) xl x low. default value: 0 (0: no interrupt, 1: x low event has occurred) table 40. la_int1_src description (continued) table 41. la_int1_ths register 0 ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 42. la_int1_ths description ths6 - ths0 interrupt 1 threshold. default value: 000 0000 table 43. la_int1_duration register 0 d6d5d4d3d2d1d0 table 44. la_int2_duration description d6 - d0 duration value. default value: 000 0000 table 45. la_int2_cfg register aoi 6d zhie zlie yhie ylie xhie xlie
LSM320HAY30 register description doc id 16917 rev 1 37/42 configuration register for interrupt 2 source. 8.18 la_int2_src (35h) table 46. la_int2_cfg description aoi and/or combination of interrupt events. default value: 0. (see table below) 6d 6 direction detection function enable. default value: 0. (see table below) zhie enable interrupt generation on z high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) zlie enable interrupt generation on z low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) yhie enable interrupt generation on y high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) ylie enable interrupt generation on y low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) xhie enable interrupt generation on x high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) xlie enable interrupt generation on x low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) table 47. interrupt mode configuration aoi 6d interrupt mode 0 0 or combination of interrupt events 0 1 6 direction move ment recognition 1 0 and combination of interrupt events 1 1 6 direction position recognition table 48. la_int2_src register 0 ia zhzlyhylxhxl
register description LSM320HAY30 38/42 doc id 16917 rev 1 interrupt 2 source register. read-only register. reading at this address clears the la_int2_src ia bit (and the interrupt signal on int 2 pin) and allows the refreshing of data in the la_int2_src register if the latched option was chosen. 8.19 la_int2_ths (36h) 8.20 la_int2_duration (37h) the d6 - d0 bits set the minimum duration of the interrupt 2 event to be recognized. duration time steps and maximum values depend on the odr chosen. table 49. la_int2_src description ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) zh z high. default value: 0 (0: no interrupt, 1: z high event has occurred) zl z low. default value: 0 (0: no interrupt; 1: z low event has occurred) yh y high. default value: 0 (0: no interrupt, 1: y high event has occurred) yl y low. default value: 0 (0: no interrupt, 1: y low event has occurred) xh x high. default value: 0 (0: no interrupt, 1: x high event has occurred) xl x low. default value: 0 (0: no interrupt, 1: x low event has occurred) table 50. la_int2_ths register 0 ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 51. la_int2_ths description ths6 - ths0 interrupt 1 threshold. default value: 000 0000 table 52. la_int2_duration register 0 d6d5d4d3d2d1d0 table 53. la_int2_duration description d6 - d0 duration value. default value: 000 0000
LSM320HAY30 package information doc id 16917 rev 1 39/42 9 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack is an st trademark. figure 11. lga-28: mechanical data and package dimensions dim. mm min. typ. max. a1 1.1 a2 0. 8 55 a 3 0.2 d1 4.25 4.4 4.55 e1 7.25 7.5 7.55 n1 0. 3 l1 5.4 l2 1. 8 p2 1.2 t1 0.6 t2 0.4 m 0.1 d 0. 3 k 0.05 h 0.1 lga-2 8 l (4.4x7.5x1.1mm) land grid array packa g e outline and 8 1 9 0050a d 1 e1 a1 p 2 l1 t2 t1 l 2 d m b e d a ? k ? k d ? k e ? k ? h c c pin 1 indicator top view seating plane n1 == a3 a2 ? k mechanical data
ordering information LSM320HAY30 40/42 doc id 16917 rev 1 10 ordering information table 54. device summary order code temperature. range [c] package [mm] packing LSM320HAY30 -40 to +85 lga-28 (4.4x7.5x1.1) tr ay LSM320HAY30tr tape and reel
LSM320HAY30 revision history doc id 16917 rev 1 41/42 11 revision history 14 table 55. document revision history date revision changes 16-dec-09 1 first issue.
LSM320HAY30 42/42 doc id 16917 rev 1 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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